Low Jitter and Multirate Clock and Data Recovery Circuit Using A Msadll for Chip-to-Chip Interconnection (Record no. 757669)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00543nab a2200133Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 230808s2004 |||||||f |||| 00| 0 eng d |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Chang, Hsiang-Hui |
| 9 (RLIN) | 759538 |
| 245 #0 - TITLE STATEMENT | |
| Title | Low Jitter and Multirate Clock and Data Recovery Circuit Using A Msadll for Chip-to-Chip Interconnection |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 2356-2364 p. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Clock and Data Recovery Circuit (Cdr) |
| 9 (RLIN) | 803342 |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Delay-Locked Loop |
| 9 (RLIN) | 768988 |
| 773 ## - HOST ITEM ENTRY | |
| Place, publisher, and date of publication | 2004 |
| Title | Ieee Transactions on Circuits and Systems, I: Fundamental Theory and Applications |
| International Standard Serial Number | 10577122 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Articles |
| -- | 51 |
| -- | ABUL KALAM Library |
| Not for loan | Home library | Serial Enumeration / chronology | Total Checkouts | Date last seen | Koha item type |
|---|---|---|---|---|---|
| Engr Abul Kalam Library | Vol.51, No.12 (Dec. 2004) | 19/08/2023 | Articles |