Low Jitter and Multirate Clock and Data Recovery Circuit Using A Msadll for Chip-to-Chip Interconnection
Chang, Hsiang-Hui
Low Jitter and Multirate Clock and Data Recovery Circuit Using A Msadll for Chip-to-Chip Interconnection - 2356-2364 p.
Clock and Data Recovery Circuit (Cdr)
Delay-Locked Loop
Low Jitter and Multirate Clock and Data Recovery Circuit Using A Msadll for Chip-to-Chip Interconnection - 2356-2364 p.
Clock and Data Recovery Circuit (Cdr)
Delay-Locked Loop