on-Chip Esd Protection Design with Substrate-Triggered Technique for Mixed-Voltage I/O Circuits in Subquarter-Micrometer Cmos Process

By: Material type: ArticleArticleDescription: 1628-1636 pSubject(s): In: Ieee Transactions on Electron Devices
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Articles Articles Periodical Section Vol.51, No.10 (Oct. 2004) Available