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Cmos Dli-Based 2-V 3.2-Ps Jitter 1-Ghz Clock Synthesizer and Temperature-Compensated Tunable Osciliator by
  • Foley, D J
  • Flynn, M.P
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A 500-Mb/S Quadruple Data Tate Sdram Interface Using a Skew Canceliation Technique by
  • Wang, Sung Ho
  • Nam, Hyoung Sik
  • Kim, Beomsup
  • Ahn, K
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A High-Resolution Cmos Time-To-Digital Converter Utilizing a Vernier Delay line by
  • Dudek, Piotr
  • Szczepanski, Stanislaw
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A 10-Gb/S Eye-Opening Monitor Ic for Decision-Guided Adaptation OfFrequency Response of an Optical Receiver by
  • Eliermeyer, Tobias
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A Low-Jitter Mixed-Mode Dli for High-Speed Dram Applications by
  • Kim, Jae-Joon
  • Lee, Sang-Bo
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
Low-Power Area-Efficient High-Speed I/O Circuit Techniques by
  • Lee, Ming-Ju Edward
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
An Ali-Analog Multiphase Delay-Locked Loop Using a Replica Delay line for Wide-Range Operation and Low-Jitter Performance by
  • Moon, Yongsam
  • Choi, Jongsang
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
Novel Automatic Tunning Method of Rc Filters Using A Digital-Dll Technique by
  • Oshima, Takayuki
  • Maio, K
  • Hioe, Willy
Source: Ieee Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
An 11-Bit High-Resolution and Adjustable-Range Cmos Time-to-Digital Converter for Space Science Instrumenys by
  • Karadamoglou, Kostas
  • Paschalidis, Nikolaos
Source: Ieee Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
Low Jitter and Multirate Clock and Data Recovery Circuit Using A Msadll for Chip-to-Chip Interconnection by
  • Chang, Hsiang-Hui
Source: Ieee Transactions on Circuits and Systems, I: Fundamental Theory and Applications
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A1-Gd/S/Pin 512-Mb Ddrii Sdram Uaing A Digital Dll and A Slew -Rate-Controlled Output Buffer by
  • Matano, Tatsuya
Source: Ieee Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A Low-Power Small-Area =7.28-Ps Jitter 1-Ghz Dll-Based Clock Generator by
  • Kim, Chulwoo
  • Hwang, In-Chul
Source: Ieee Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
Jitter Transfer Charateristics of Delay-Locked Loops-Theories and Design Techniques by
  • Lee, M.-J Edward
Source: Ieee Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A Low-Jitter Wide -Range Skew-Calibrated Dual-Loop Dll Using Antifuse Circuitry for Figh-Speed Dram by
  • Kim, Se Jun
  • Hong, Sang Hoon
  • Wee, Jae-Kyung
  • Cho, Joo Hwan
Source: Ieee Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A 900-Mb/S Cmos Data Recovery Dll Using Half-Frequency Clock by
  • Maillard, Xavier
  • Devisch, Frederic
  • Kuijk, Maarten
Source: Ieee Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
Vinration-to-Electric Energy Conversion by
  • Meninger, S
  • Mur-Miranda, J. O
  • Amirtharajah, R
  • Chandrakasan, A
Source: Ieee Transactions on Very Large Scale Intergration (Vlsi) Systems
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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