A Bit-Level Pipelined Vlsi Rchitectures for Running Order Algorithm. (Record no. 799307)
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000 -LEADER | |
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fixed length control field | 00422nab a2200133Ia 4500 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 230808s1997 |||||||f |||| 00| 0 eng d |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Hsiao, J. H |
9 (RLIN) | 858056 |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Chen, C. T |
9 (RLIN) | 858057 |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Chen, L. G |
9 (RLIN) | 764781 |
245 #2 - TITLE STATEMENT | |
Title | A Bit-Level Pipelined Vlsi Rchitectures for Running Order Algorithm. |
300 ## - PHYSICAL DESCRIPTION | |
Extent | 2140-2144 p. |
773 ## - HOST ITEM ENTRY | |
Place, publisher, and date of publication | 1997 |
Title | Ieee Transactions on Signal Processing |
International Standard Serial Number | 1053587X |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Koha item type | Articles |
-- | 51 |
-- | ABUL KALAM Library |
Not for loan | Home library | Serial Enumeration / chronology | Total Checkouts | Date last seen | Koha item type |
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Engr Abul Kalam Library | Vol.45, No.08 (Aug. 1997) | 20/08/2023 | Articles |