000			00417nab a2200121Ia 4500
008			230808s2003 |||||||f |||| 00| 0 eng d
100			_aMatano, Tatsuya _9813459
245		0	_aA1-Gd/S/Pin 512-Mb Ddrii Sdram Uaing A Digital Dll and A Slew -Rate-Controlled Output Buffer
300			_a762-768 p.
650			_aDelay-Locked Loop _9768988
773			_d2003 _tIeee Journal of Solid-State Circuits _x00189200
942			_cART _o51 _pABUL KALAM Library
999			_c765629 _d765629