| 000 | 00543nab a2200133Ia 4500 | ||
|---|---|---|---|
| 008 | 230808s2004 |||||||f |||| 00| 0 eng d | ||
| 100 |
_aChang, Hsiang-Hui _9759538 |
||
| 245 | 0 | _aLow Jitter and Multirate Clock and Data Recovery Circuit Using A Msadll for Chip-to-Chip Interconnection | |
| 300 | _a2356-2364 p. | ||
| 650 |
_aClock and Data Recovery Circuit (Cdr) _9803342 |
||
| 650 |
_aDelay-Locked Loop _9768988 |
||
| 773 |
_d2004 _tIeee Transactions on Circuits and Systems, I: Fundamental Theory and Applications _x10577122 |
||
| 942 |
_cART _o51 _pABUL KALAM Library |
||
| 999 |
_c757669 _d757669 |
||