000			00537nab a2200157Ia 4500
008			230808s2000 |||||||f |||| 00| 0 eng d
100			_aDudek, Piotr _9769467
100			_aSzczepanski, Stanislaw _9769468
245		2	_aA High-Resolution Cmos Time-To-Digital Converter Utilizing a Vernier Delay line
300			_a240-247 p.
650			_aDelay-Locked Loop _9768988
650			_aTime of Flight _9752903
650			_aTime-To-Digital Converter _9715176
773			_d2000 _tIEEE Journal of Solid-State Circuits _x00189200
942			_cART _o51 _pABUL KALAM Library
999			_c740712 _d740712