IEEE Micro:The Magazine for Chip & Silicon Systems Designers
Material type:![Continuing resource](/opac-tmpl/lib/famfamfam/SE.png)
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Item type | Current library | Collection | Shelving location | Call number | Vol info | Status | Notes | Date due | Barcode |
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Periodical Section | Department of Computer & Information Systems Engineering | Periodical Section | Vol.22, No.06 (Nov. 2002) | Not For Loan | Bimonthly | S5147 | ||
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Periodical Section | Department of Computer & Information Systems Engineering | Periodical Section | Vol.22, No.05 (Sep. 2002) | Not For Loan | Bimonthly | S4642 | ||
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Periodical Section | Department of Computer & Information Systems Engineering | Periodical Section | Vol.22, No.04 (Jul. 2002) | Not For Loan | Bimonthly | S3502 | ||
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Periodical Section | Department of Computer & Information Systems Engineering | Periodical Section | Vol.22, No.03 (May. 2002) | Not For Loan | Bimonthly | S3501 | ||
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Periodical Section | Department of Computer & Information Systems Engineering | Periodical Section | Vol.22, No.02 (Mar. 2002) | Not For Loan | Bimonthly | S2472 | ||
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Periodical Section | Department of Computer & Information Systems Engineering | Periodical Section | Vol.22, No.01 (Jan. 2002) | Not For Loan | Bimonthly | S2421 |
Systems on A Chip:Next Electronic Frontier by
Source: Ieee Micro:The Magazine for Chip & Silicon Systems Designers
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Chain: A Delay-Insensitive Chip Area Interconnect by
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Coping with Latency in Soc Design by
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An Interconnect Architecture for Networking Systems on Chips by
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A Scalable High-Performance Computing Solution for Networks on Chips by
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A Polymorphous Computing Fabric by
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A Neirarchical Test Methodology for Systems on Chip by
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Efficient Construction Aliasing -Free Compaction Circuitry by
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Efficient Randomized Algorithms for Input -Queued Switch Scheduling by
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An Implmentable Parallel Schedular for Inpu-Queed Switches by
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The Alpha 21364 Network Architecture by
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The Sun Fireplane Interconnect by
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The Quadris Networks : High Performance Clustering Technology by
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Routing Table Compaction in Ternary Cam by
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Protocol Wrappers for Layered Network Npacket Processing in Reconfigurable Hardware by
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Maintaining Statistics Counters in Router Line Cards by
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Tcp Switching : Exposing Circuits to Ip by
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Sdaarc: An Extended Cache-only Memory Architecture by
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Guest Editor'S Introduction: Critical Embedded Automotive Networks by
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Design and Analysis of A Robust Real-Time Engine Control Network by
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Can for Critical Embedded Automotive Networks by
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Time-Triggered Architecture: A Consistent Computing Plat for m by
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The Ftt-Can Protocol for Flexibility in Safety-Critical Systems by
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Model-Based System Development An Approach to Building X-By-Wire Applications by
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The Basics of Performance-Monitoring Hardware by
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Pentium 4 Performance-Monitoring Features by
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Which Industries UseInternet by
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Standardization and Competitive Advantage by
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Making Computers Invisible by
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Mica: A Wireless Plat for m for Deeply Embedded Networks by
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Guest Editor'S Introduction: Unrthodox Computer Architectures by
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Ulsi Architectures for Artificial Neural Networks by
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A Parallel Neural Processor for Real-Time Applications by
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Intelligent-Momory Architecture for Artifical Neural Networks by
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Learning Hardware Using Multiple-Valued Logic Part 1: Introduction and Approach by
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Learning Hardware Using Multiple-Valued Logic Part 2: Cube Calculus and Architecture by
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Ubiquitous Spataialin for mation Services Using Cell Phones by
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T-Engine:Open,Real-Time Embedded-Systems Plat for m by
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Data Communication in Systems with Heterogeneous Timing by
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Dataplay'S Mobile Information Distribution and Storage Technology by
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Power4 System Design for High Reliability by
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The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs by
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Intel 870: A Building Block for Cost-Effective, Scalable Servers by
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Infinibridge: An Infiniband Channel Adapter with Integrated Switch by
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Access-Mode Pridictions for Low-Power Cache Design by
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