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A Fuliy Integrated 40-Gb/S Clock and Data Recovery Ic with 1:4 Demux in Sige Technology by
  • Reinhold, Mario
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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Corrections to "Analysis of A Half-Rate Bang-Bang Phase-Locked Loop" by
  • Ramezani, M
  • Salama, C. A. T
Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing)
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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Analysis of A Half-Rate Bang-Bang Phase-Locked-Loop by
  • Ramezani, M
Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing)
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
Request article
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