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		A 0.6-2.5-Gbaud Cmos Tracked 3Oversampling Transceiver with Dead-Zone Phase Detection for Robust Clock/Data Recovery by Moon, Yongsam Jeong, Deog-Kyoon Source: IEEE Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan:* Engr Abul Kalam Library (1). Request article
		A Cmos Clock Recovery Circuit for 2.5-Gb/S Nrz Data by Anand, Seema Butala Razavi, Behzad Source: IEEE Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 2.5-Ghz Four-Phase Clock Generator with Scalable No-Feedback-Loop Architecture by Yamaguchi, Kouichi Fukaishi, Muneo Source: IEEE Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A Semi Digital Delay Locked Loop Using An Analog Based Finite State Machine by Friedman, Daniel Rhee, Woogeun Parker, Benjamin Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 33-Mw 8-Gb/S Cmos Clock Multiplier and Cdr for Highly Integrated I/Os by Farjad-Rad, Ramin Nguyen, Anhtuyet Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A Cmos 10-Gd/S Sonet Transceiver by Muthali, Harish S Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 10-Gb/S Sonet-Complaint Cmos Transceiver with Low Crosstalk and Intrinsic Jitter by Werker, Heinz Meching, Stephan Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 2.5-10-Gb/S Cmos Transceiver with Alternating Edge-Sampling Phase Detection for Loop Characteristic Stabilization by Hwang, Moon-Sang Jeong, Deog-Kyoon Lee, Bong-Joon Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 10-Gb/S Cmos Clock and Data Recovery Circuit with A Half-Rate Binary Phase/Frequency Detector by Razavi, Behzad Savoj, Jafar Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 4-Gb/S Cmos Clock and Data Recovery Circuit Using 1/8-Rate Clock Technique by Song, Seong-Jun Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Loop-Based Interconnect Modeling and Optimization Approach for Multigigahertz Clock Network Design by Huang, X Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article

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