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		System Level Exploration for Patero by Givargis, T. D Source: Ieee Transactions on Very Large Scale Intergration (Vlsi) Systems Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Induction -Base System-Level Power Evaluation of System-on-A-Chip Peripheral Cores by Givargis, T. D Vahid, F Source: Ieee Transactions on Very Large Scale Intergration (Vlsi) Systems Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Evaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-A-Chip Designs by Givargis, T. D Henkel, J Vahid, F Source: Ieee Transactions on Very Large Scale Intergration (Vlsi) Systems Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article

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