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A Dual 10-B 200-Msps Pipelined D/A Convereter with Dll-Based Clock Synthesizer by
  • Manganaro, G
  • Kwak, Sung-Ung
Source: Ieee Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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A Behavioral Modeling Approach toDesign of A Low Jitter Clock Source by
  • Kwak, Sung-Ung
  • Manganaro, Gabriele
  • Cho, Seonghwan
Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing)
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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