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Cmos Implementation of a Multiple-Valued Logic Signed-Digit Fuli Adder Based on Negative-Differential-Resistance Devices by
  • Gonzalez, Alejandro F
  • Bhattacharaya, M
  • Kulkarni, Shriram
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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Noise Margins of Threshold Logic Gates Containing Resonant Tunneling Diodes. by
  • Mazumder, P
  • Bhattacharaya, M
Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing)
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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