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Area-Efficient Qc-Ldpc Decoder Architecture Based on Stride Scheduling and Memory Bank Division by
  • Kim, Bongjin
  • Park, In-Cheol
Source: IEICE Transactions on Communications
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A Third-Order Modulator in 0.18-M Cmos with Calibrated Mixed-Mode Integrators by
  • Shim, Jae Hoon
  • Park, In-Cheol
Source: IEEE Journal of Solid-State Circuits
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
A Low Power Variable Length Decoder for Mpeg 2 Based on Successive Decoding of Short Codewords by
  • Lee, Sung-Won
  • Park, In-Cheol
Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing)
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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