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Electrical Test Strategies for A Wafer-Level Packaging Technology by
  • Keezer, David C
  • Patel, Chirag S
  • Bakir, Muhannad S
  • Zhou, Qing
Source: Ieee Transactions onElectronics Packaging Manufacturing
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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Sea of Leads (Sol) Ultrahigh Density Wafer-Level Chip Input/Output Interconnections for Gigascale Integration by
  • Bakir, Muhannad S
  • Reed, Hollie A
  • Kohl, Paul A
Source: Ieee Transactions on Electron Devices
Material type: Article Article; Format: print
Availability: Items available for loan: Engr Abul Kalam Library (1).
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