Hwang, W. Chaung, C.T. Curran, B.W Rosenfield, M.G. <br/><br/>
Performance Analysis of Tapered Gate in Pd/Soi Cmos Technology. 

 - 267-275 p. 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Pd/Soi (Partially Depleted Silicion -Insulator Technology)<br/>Cmos Technology<br/>Cmos Microprocessors