TY  - SER
AU  - Ishii, Kiyoshi
AU  - Enoki, Takatomo
AU  - Shibata, Tsugumichi
TI  - A 10-Gb/S Data-Pattern Independent Clock and Data Recovery Circuit with A Two-Mode Phase Comparator
KW  - Clock and Data Recovery (Cdr)
KW  - Phase-Locked Loop (Pll)
KW  - Jitter Generation
ER  -