Chang, Hsiang-Hui <br/><br/>
Low Jitter and Multirate Clock and Data Recovery Circuit Using A Msadll  for  Chip-to-Chip Interconnection 

 - 2356-2364 p. 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Clock and Data Recovery Circuit (Cdr)<br/>Delay-Locked Loop