TY  - SER
AU  - Gyvez, Jose Pineda De
AU  - Tuinhout, Hans P.
TI  - Threshold Voltage Mismatch and Intre-Die Leakage Current in Digital Cmos Circuits
KW  - Leakage Currents
KW  - Mismatch
KW  - Subthreshold Logic
ER  -