Dual -Vt Self-Timed Cmos Logic for Low Subthreshold Current Multigigabit Synchronous Dram.

By: Material type: ArticleArticleDescription: 1263-1271 pSubject(s): In: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing)
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Articles Articles Periodical Section Vol.45, No.09 (Sep. 1998) Available