A 66-333-Mhz 12-Mw Registrar-Controlled Dll with A Signal Delay Line and Adaptive -Duty-Cycle Clock Dividers for Production Ddr Sdrams

By: Material type: ArticleArticleDescription: 2087-2092 pSubject(s): In: Ieee Journal of Solid-State Circuits
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Articles Articles Periodical Section Vol.39, No.11 (Nov. 2004) Available