1.8-V 800-Mb/S/Pin Ddr2 and 2.5-V 400-Mb/S/Pin Ddr1 Compatibly Designed 1-Gb Sdram with Dual-Clock Input-Latch Scheme and Hybrid Multi-Oxide Output Buffer

By: Material type: ArticleArticleDescription: 862-869 pSubject(s): In: IEEE Journal of Solid-State Circuits
Holdings
Item type Current library Call number Vol info Status Date due Barcode
Articles Articles Periodical Section Vol.40, No.04 (Apr. 2005) Available