Electronics Engineering Development and Verification of Soft IP Core of Usb 3.0 in Verilog HDL a Project Submitted to the NED university of Engineering and Technology in Partial Fulfillment for the Degree of Bachelor of Electronics Engineering
Material type:![Text](/opac-tmpl/lib/famfamfam/BK.png)
- 621.3985378242 NED
Item type | Current library | Shelving location | Call number | Status | Date due | Barcode |
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Government Document Section | Govt Publication Section | 621.3985378242 NED | Available | 91711 |