Ant-on Yards: Fpga/Mpu Hybrid Architecture for Telecommunications Data Processing. (Record no. 796978)

MARC details
000 -LEADER
fixed length control field 00522nab a2200145Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 230808s1998 |||||||f |||| 00| 0 eng d
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Miyazaki, T
9 (RLIN) 765073
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Tsutsui, A
9 (RLIN) 855646
245 #0 - TITLE STATEMENT
Title Ant-on Yards: Fpga/Mpu Hybrid Architecture for Telecommunications Data Processing.
300 ## - PHYSICAL DESCRIPTION
Extent 199-211 p.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Codesign
9 (RLIN) 835648
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Field Programmable Gate Arrary (Fpga)
9 (RLIN) 748879
773 ## - HOST ITEM ENTRY
Place, publisher, and date of publication 1998
Title Ieee Transactions on Very Large Scale Intergration (Vlsi) Systems
International Standard Serial Number 10638210
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Articles
-- 51
-- ABUL KALAM Library
Holdings
Not for loan Home library Serial Enumeration / chronology Total Checkouts Date last seen Koha item type
  Engr Abul Kalam Library Vol.06, No.02 (Jun. 1998)   20/08/2023 Articles