Design Verification of Fpga Implementations. (Record no. 789870)

MARC details
000 -LEADER
fixed length control field 00524nab a2200169Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 230808s1999 |||||||f |||| 00| 0 eng d
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Chen, Xiao-Tao
9 (RLIN) 847220
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Huang, Wei-Kang
9 (RLIN) 847222
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Park, Nohpill
9 (RLIN) 809065
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name J.Meyer, Fred
9 (RLIN) 847224
245 #0 - TITLE STATEMENT
Title Design Verification of Fpga Implementations.
300 ## - PHYSICAL DESCRIPTION
Extent 66-73 p.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Design & Test of Computers
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Design Verification
9 (RLIN) 779063
773 ## - HOST ITEM ENTRY
Place, publisher, and date of publication 1999
Title Ieee Design and Test of Computers
International Standard Serial Number 07407475
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Articles
-- 51
-- ABUL KALAM Library
Holdings
Not for loan Home library Serial Enumeration / chronology Total Checkouts Date last seen Koha item type
  Engr Abul Kalam Library Vol.16, No.02 (Apr. 1999)   20/08/2023 Articles