Sub 1 V Design Techniques for High Linearity Multistage Pipelined Analog to Digital Converters (Record no. 751034)

MARC details
000 -LEADER
fixed length control field 00597nab a2200157Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 230808s2005 |||||||f |||| 00| 0 eng d
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Chang, Dong-Young
9 (RLIN) 792822
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Ahn, Gil-Cho
9 (RLIN) 758273
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Moon, Un-Ku
9 (RLIN) 759847
245 #0 - TITLE STATEMENT
Title Sub 1 V Design Techniques for High Linearity Multistage Pipelined Analog to Digital Converters
300 ## - PHYSICAL DESCRIPTION
Extent 01-12 p.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Ultra-Low Voltage
9 (RLIN) 792823
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Analog-to-Digital Converter(Adc)
9 (RLIN) 792825
773 ## - HOST ITEM ENTRY
Place, publisher, and date of publication 2005
Title Ieee Transactions on Circuits and Systems, I: Fundamental Theory and Applications
International Standard Serial Number 10577122
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Articles
-- 51
-- ABUL KALAM Library
Holdings
Not for loan Home library Serial Enumeration / chronology Total Checkouts Date last seen Koha item type
  Engr Abul Kalam Library Vol.52, No.01 (Jan. 2005)   19/08/2023 Articles