Analytical Threshold Voltage Modeling of Surrounding Gate Ksilicon Nanowire Transistors with Didfferent Geometries (Record no. 712475)

MARC details
000 -LEADER
fixed length control field 00634nab a2200157Ia 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 230808s2014 |||||||f |||| 00| 0 eng d
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Pabdian, M. Karthigai
9 (RLIN) 708226
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Balamurugan, N. B.
245 #0 - TITLE STATEMENT
Title Analytical Threshold Voltage Modeling of Surrounding Gate Ksilicon Nanowire Transistors with Didfferent Geometries
300 ## - PHYSICAL DESCRIPTION
Extent 2079-2088 p.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Junction Based Cylindrical Surrounding Gate Silicon Nanowire Transistor
9 (RLIN) 708227
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Drain Bias
9 (RLIN) 708228
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Channel Length Modulation
9 (RLIN) 708229
773 ## - HOST ITEM ENTRY
Place, publisher, and date of publication 2014
Title Journal of Electrical Engineering and Technology
International Standard Serial Number 19750102
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Articles
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Not for loan Home library Serial Enumeration / chronology Total Checkouts Date last seen Koha item type
  Engr Abul Kalam Library Vol.09, No.06 (Nov. 2014)   19/08/2023 Articles