A 10-Gb/S Data-Pattern Independent Clock and Data Recovery Circuit with A Two-Mode Phase Comparator
Ishii, Kiyoshi Enoki, Takatomo Shibata, Tsugumichi
A 10-Gb/S Data-Pattern Independent Clock and Data Recovery Circuit with A Two-Mode Phase Comparator - 192-197 p.
Clock and Data Recovery (Cdr)
Phase-Locked Loop (Pll)
Jitter Generation
A 10-Gb/S Data-Pattern Independent Clock and Data Recovery Circuit with A Two-Mode Phase Comparator - 192-197 p.
Clock and Data Recovery (Cdr)
Phase-Locked Loop (Pll)
Jitter Generation